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What is a CPU?

The purpose of this document is to provide a basic overview of underlying technologies and operating principles of a Central processing unit

It is beyond the scope of this document to provide any specific technical information related to any commercial product. A general introduction to the topic of Central processing units will be presented below and in conjunction with the attached ‘Powerpoint’ presentation.

It is difficult to discuss the Central processing unit without placing it in some kind of context. There are many historical land marks that mark the path of the Central processing unit to the present day. However, one name is link closely with the origins of the Central processor unit’s development, John Von Nuemann. He is probably best known for his work on developing computer systems but without his efforts the modern Central processing unit could have been very difficult.

Von Nuemann, 1903-1957(O'Connor, J. Robertson, E. 2003), Hungarian mathematician postulated the design of a device which could calculate instructions but more importantly store the instructions in memory. The Von Nuemann computer model described: an arithmetic logic unit, processor registers, control unit, linked to external memory to store the information/ data and input/ output devices such as keyboard and display (Null, L. Lobur, J. 2006. pg. 32).

Underlying technology 

What is a CPU?

A Central processing unit contains a set of discrete components, although the quantity and type may change a cross devices, in general Central processor units have the following items:

 

Control Unit

To manage the flow of information and data within the Central processing unit a ‘Control Unit’ is required (as defined by Von Nuemanns model). The control unit is sometimes referred to as a ‘brain within a brain’. It is an extremely complex component of the CPU and is better understood if it is divided in the three main tasks that it performs: decoding instructions, timer/ clock keeping track of time and control logic used to order the flow of signals through the Central processing unit (Eastaugh, M. 2004). The actual function of the control unit varies dependant of the type of Central processing unit but in general (x86 type Central processing unit) it performs the instruction set: fetch, decode, execute and data flow between registers (this is a simplified description). Think of the control unit as the conductor of an orchestra.

 

Arithmetic Logic Unit

The Arithmetic logic unit performs logic and arithmetic operations passed to it be the Central processor units registers. The Arithmetic logic unit works with integers performing calculation and comparing data using boolean operations (Henderson, H. 2008. pg. 23). Any floating point operations are handled by a Floating point unit (beyond the scope of the document). The Arithmetic Logic Unit operates on an input size referred to as 'word' length. Many modern Central processor units have word lengths of 8, 16, 32 and 64 bit. Word length is the number of bits a CPU can process at once. B. Ram (2000) states the following with regards to word length:

“A digital computer operates on binary digits, 0 and 1. It can understand information only in terms of 0s and 1s. As already mentioned binary is called a bit. The word bit is the short form of binary digit. A group of 8 bits is called a byte. The number of bits that a computer can process at a time in parallel is called its word length.”

 

Some examples of the operations performed by a general purpose Arithmetic logic unit or ALU for short are:

Addition

Subtraction

Multiplication

Division

Logical AND

Logical OR etc.

 

Registers

Built directly into the Central processing unit, registers are fast read/ write circuits. Used to store and write data from the arithmetic logic unit and control unit. Typical they number around 32 bits but this may vary and the size is restricted to 32, 64, 80, 128 bits. The type and quantity of registers is specific to each type and model of Central processing unit, however, some examples are (Eastaugh, M. 2004 ):

Memory address register (MAR)- Holds the memory address of the instructions to be read.

Memory data register (MDR)- Holds the data fetched from memory or which is to be stored in memory.

Instruction register (IR)- Holds the instruction currently being decoded, prepared and executed.

Program counter (PC)- Holds the current position in the instruction set.

General purpose registers- Reduces the need to read and write to slower system memory. An example is the accumulator which stores the results of operations.

 

It is worth explaining the Accumulator in more detail. Use as a general-purpose register that is used for arithmetic and logical operations, Mansour, N. (2000) says:

 

“The accumulator can be loaded with data from a memory location, or its data can be stored in a memory location. The number held in the accumulator can be added to, subtracted from, or compared with another number from memory. The accumulator is the basic work register of a computer. It is commonly called the 'A register'.”

 

 

Cache

The Central processing unit accesses data at high speed, much faster than the computer systems memory. To allow this fast access the Central processing unit has cache memory. Modern processors have several levels of cache used to perform different tasks by the Central processing unit. Level 1 cache is generally very small (ranging from 2 kilobytes to 64 kilobytes) with Level 2 etc. situated off the Central processing unit. With advancements in CPU technology the inclusion of additional caches has increase. These additional caches are used to minimise bottlenecks in the machine cycle (fetch, decode, execute store).

 

Backstore

Although back storage is not part of the Central processing unit it is worth understanding it’s relationship to the processor. Back store memory has to be non-volatile so that it does not loss its content if power is lost. Examples of back storage would be: hard disk drive, CD/ DVD Drive, USB pen drive etc.

 

Bus

The CPU communicates with the rest of the PC using buses. There are three main buses: Control, Data and Address. Often described as the highways where data travels around the PC system.

 

Additional Central processing unit information

 

Clock

A Central processing unit has a clock speed which is defined as the frequency of processor executes. The clock speed is measured in millions of cycles per second also referred to as: megahertz. The clock is a quartz crystal that vibrates at a certain frequency, megahertz, when it is conducting electricity. Each vibration sends out a pulse to each component of the CPU that synchronised with it (PC Computer Notes, 2003).

 

Architecture differences

Central processors or CPU's are produced in many different varieties and each processor has a specific set of components to perform a specific task. A list of CPU types (Carmello, J., Clifton, A. & Yu, J. 2010):

 

CISC - Complex Instruction Set Computing

RISC - Reduced Instruction Set Computing

MIPS - Microprocessor without Interlocked Pipeline Stages

MISC - Minimal Instruction Set Computer

OISC - One Instruction Set Computer

URISC - Ultimate Reduced Instruction Set Computer

NISC – No Instruction Set Computer

ZISC – Zero Instruction Set Computer

VLIW - Very Long Instruction Word

 

Basically, the difference between each of the CPU types is how they handle instructions and what type of instructions they accept. The type main types of CPU presently in use are RISC and CISC. With regard to the CISC architecture, Knight, J. (2006) states:

 

“CISC (Complex Instruction Set Computer) is a retroactive definition that was introduced to distinguish the design from RISC microprocessors. In contrast to RISC, CISC chips have a large amount of different and complex instruction. The argument for its continued use indicates that the chip designers should make life easier for the programmer by reducing the amount of instructions required to program the CPU.”

 

RISC however is described by Computer Architecture (2002) as:

 

“The advantage of RISC CPU's is that their control units are much simpler. Moreover as we shall see, pipelining requires RISC architecture. The pentium translates CISC to RISC on chip in order to perform pipelining. Our example will have 16 user registers numbered R0 to R15. It will also have a stack pointer SP, and PUSH will decrease SP. Generally, RISC CPU's have many more user registers than a Pentium. A 32 bit Risc CPU may have 128, or even 256 user registers. Assembly mnemonics will be those of INTEL. They will be of the form OP Destination_Register Source_Register, Eg MOV R1, R2.”

 

 

Operating Principles

 

Machine Cycle

The Central processing unit continually performs a cycle where it receives an instruction from the program code, decodes that instruction, performs the action required in the instruction and then looks for the next instruction – the CPU fetches the instruction, decodes and then executes the instruction, this is called the Machine cycle or Instruction cycle. The four stages of the machine cycle are:

 

Fetch Cycle

The contents of the Program counter, this is the location of the next instruction, are copied into the Memory address register. The contents of memory at the location designated by the MAR are checked by the Control unit then copied into the Memory data register and the Program counter is incremented by the number of bytes which make up an instruction. The contents of the Memory data register are copied into the Instruction register.

 

Decode Cycle

Content (the instruction) from the Instruction register is sent to the Control unit. There it is examined to see what the instruction is requesting. From this analysis the Control unit will forward the instruction to the correct circuit in the Central processing unit.

 

Execute Cycle

Once the instruction has reach the appropriate circuit the instruction is performed and the cycle continues until the instruction set is complete.

This cycle can be expressed in pseudo code, as illustrated by King, P. (1999):

 

            “set instruction address to the address of the first instruction

             while program not finished

                        {

                       fetch instruction from current instruction address

                       update current instruction address

                       execute the fetched instruction

                         }”

 

Instruction format

Having examined the Fetch, decode, execute cycle we now need to know what an instruction is. Fundamentally, it is the smallest command that can be passed to a CPU. The way all the different operations are encoded into binary is called the 'Instruction format'. An instruction contains two types of information the opcode and the operand. The opcode has a mnemonic for the binary machine code which in turn is the language CPU's communicate with. Clements, A. (2006, pg. 211) describes Instructions as:

 

“classified by type (what they do) and by the number of operands they take. The three basic instruction types are data movement which copies data from one location to another, data processing, which operates on data, and flow con- trol, which modifies the order in which instructions are exe- cuted.”

 

An operand is the information, or address of the information, which is being operated on (Hand, C. no date).

 

An example of this is the Subtract Instruction (Hand, C. no date):

 

fetch operand, store in register location 'A'

fetch operand, store in register location 'B'

Instruct the Arithmetic logic unit to subtract A from B

Place the result in the accumulator register

  

References

 

B. Ram (2000) Computer Fundamentals: architecture and organization. New Age International (P) ltd., India

 

Carmello, J. Clifton, A. Yu, J. (2010) 'Computer Architecture'. [online] Available at: http://www.academic.marist.edu/~jzbv/architecture/Projects/mainframe.ppt [accessed: 10th Mar 2012]

 

Clements, A. (2006) Principles of Computer Hardware. Oxford University Press, United Kingdom

 

Computer Architecture. (2002) 'CPU Architecture' [online] Available at: http://www.dcs.bbk.ac.uk/~jkg/arch5.doc [accessed: 10th Mar 2012]

 

Eastaugh, M. (2004) 'Control Unit'. [online] Available at: http://www.eastaughs.fsnet.co.uk/cpu/structure-cu.htm  [accessed: 28th Feb 2012]

Null, L. Lobur, J. (2006) The Essentials of Computer Organization and Architecture. Jones and Bartlett Publishers, Canada

 

Eastaugh, M. (2004) 'Microprocessor Tutorial'. [online] Available at:http://www.eastaughs.fsnet.co.uk/cpu/structure-reg.htm [accessed: 10th Mar 2012]

 

Hand, C. (no date) 'Instruction execution'. [online] Available at:http://www.cse.dmu.ac.uk/Modules/CSYS/CSYS1001/lec9/c1001-l9.html [accessed: 9th Mar 2012]

 

Henderson, H. (2008) Encyclopedia of Computer Science and Technology. Facts on File, United States of America

 

King, P. (1999) 'The execution cycle'. [online] Available at: http://www.macs.hw.ac.uk/~pjbk/pathways/cpp1/node16.html [accessed: 10th Mar 2012]

 

Knight, J. (2006) 'CISC Vs. RISC' [online] Available at: http://www.amigahistory.co.uk/riscisc.html [accessed: 10th Mar 2012]

O'Connor, J. Robertson, E. (2003) 'John von Neumann'. [online] Available at: http://www.gap-system.org/~history/Biographies/Von_Neumann.html [accessed: 1st Mar 2012]

 

PC Computer Notes (2003) 'Clock Speed'. [online] Available at: http://www.pccomputernotes.com/clockspeed/clockspeed.htm [accessed: 10th Mar 2012]

 

Virginia Tech. 'Machine Architecture'. [online] Available at: http://courses.cs.vt.edu/csonline/MachineArchitecture/Lessons/CPU/Lesson.html [accessed: 3rd Mar 2012]

 


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